Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes configurable logic blocks (CLBs), programmable input/output blocks (IOBs), and other types of logic blocks, such as memories, microprocessors, digital signal processors (DSPs), and the like. The CLBs, IOBs, and other logic blocks are interconnected by a programmable interconnect structure. The CLBs, IOBs, logic blocks, and interconnect structure are typically programmed by loading a stream of configuration data (known as a bitstream) into internal configuration memory cells that define how the CLBs, IOBs, logic blocks, and interconnect structure are configured. An FPGA may also include various dedicated logic circuits, such as digital clock managers (DCMs), input/output (I/O) transceivers, boundary scan logic, and the like.
As semiconductor technology has advanced, the amount and speed of logic available on an IC, such as an FPGA, has increased more rapidly than the number and performance of I/O connections. As a result, IC die stacking techniques have received renewed interest to address the interconnection bottleneck of high-performance systems. In stacked IC applications, two or more ICs are stacked vertically and interconnections are made between them.
One approach to stacking a die on an FPGA involves mounting a second die on the face side of the FPGA die. The term “face side” denotes the side of a FPGA die that receives the bulk of semiconductor processing such that circuitry and interconnect are fabricated on that face side. The FPGA includes interface circuitry coupled to an array of contacts on the face side of the FPGA die. A second die is mounted on the face side of the FPGA die such that signals from the second die are communicated through the contacts to the interface circuitry of the FPGA. This approach, however, is incompatible with FPGAs designed for flip-chip packaging. In a flip-chip package, the bump contacts for power, ground, and signals are distributed throughout the face side of the FPGA die. Such bump contacts make it difficult if not impossible to mount a second IC to the face side of the FPGA die. Accordingly, there exists a need in the art for a die stacking approach that is compatible with flip-chip integrated circuit packaging techniques.